XP-SISR: Eingebaute Selbstdiagnose für Schaltungen mit Prüfpfad

The advantages of Built-In Self-Test (BIST) are well known, and for embedded memories BIST is already the preferred test method. However, for random logic BIST is less often employed. This is mainly due to the following two reasons: On the one hand, deterministic patterns might be necessary to achieve reasonable fault coverage, yet they are expensive in built-in tests. On the other hand, the diagnostic information provided by BIST-signatures is rather poor. During the last years the first issue has been tackled successfully. This paper deals with the second issue. A new method for Built-In Self-Diagnosis (BISD) is presented. The method’s backbone is a combination of extreme space and time compaction, which for the first time allows to store the expected test responses and the failing test responses with negligible overhead on chip. Consequently, all data relevant to diagnosis can be collected during a single self-test session. The BISD method additionally comprises a diagnosis algorithm and a test pattern generation scheme, which overcome aliasing and the reduced diagnostic resolution introduced by the extreme compaction. Experiments with recent, industrial designs demonstrate, that diagnostic resolution is maintaned compared to external testing and the additional hardware needed to implement the BISD-scheme is negligibly small. Schlüsselwörter /